Integrated circuits are typically fabricated on a wafer of silicon or other appropriate semiconductor. After fabrication of a wafer, the individual chips are separated from the wafer and packaged and interconnected with other circuits in their final application, such as for computers, consumer electronics, etc.
In order to function as intended, the chips of integrated circuits are provided with external electrical connections for use with other circuits. In some designs, certain of the external connections are typically formed by plating metal pads on the bottom (backside) of the wafer.
When the die are separated, the backside metal (BM) must be separated along with the semiconductor chips. Typical die separation techniques involve sawing or scribe and break. These techniques involve either grinding away or cleaving the semiconductor wafer to separate the die.
The results of these separation techniques are sensitive to the mechanical properties of the material being separated. Because semiconductors tend to be hard and brittle, while the metal (e.g., Au/Ge—NI—Au) of the connections is soft and ductile, the BM layer is often damaged (e.g., torn, delaminated, etc.) when the die are separated.
Scribing and breaking wafers often causes the BM layer to tear across a break line. Sawing often causes small chips to be dislodged adjacent the saw kerf, thereby loosening the edges of the BM layer adjacent the saw kerf.
Wafers are generally mounted on adhesive tape (saw frames) before die separation. After separation, the die are then removed from (i.e., picked off) the tape and either placed in their final package or in an intermediate carrier. As the die are removed from the adhesive, the damaged edges adhere to the tape, peel off the die and/or form burrs.
The metal burrs on the bottom of the die cause misalignment during use by causing the die to rest at an angle when placed on a flat surface. When placed into a final package the misalignment of the top surface of the die can degrade the performance of devices optically connected with the die.
In addition, the tilted die degrades the quality of wire bonds and reduces the ability of the package to extract heat from active devices. Both conditions can cause long-term quality and reliability concerns.
Peeled metal and tilted die can reduce the electrical contact area thereby increasing die electrical resistance. Because the tearing process is inherently random, tearing contributes to process variability in integrated circuit production and use.
In addition, the trend towards smaller die increases the variability caused by torn and/or delaminated metal. For example, for any given metal burr height, a smaller die width will cause a larger tilt angle. For a given area of torn metal, the smaller die will also result in a greater percentage of total area being damaged.
As die sizes shrink, the tackiness of the tape used during dicing must also be increased to keep the die attached to the tape during dicing. The increased tackiness increases the incidence of damage. Consequently, a need exists for a methods and apparatus for reducing the incidence of damaged electrical contacts during the separation process.